Integrated circuit designs require testing to ensure proper functioning of all logic components. However, as the size and number of the logic components on the integrated circuit continues to increase, the number of multiple clocks activating the logic components has also increased.
In typical integrated circuit designs, a clock domain is defined as a set of memory components, e.g., flip-flops, registers, synchronous RAM, etc. The clock domains may exchange data, and the point at which the clock domains exchange the data may be referred to as a clock domain crossing. Clock domains that exchange data need to be interfaced and synchronized in reliable and predictable manners to ensure the proper transfer of data from one clock domain to another.
One method for testing the clock domains to ensure the proper transfer of data from one clock domain to another is to test each clock domain one at a time. However, this method can be very inefficient, time consuming, and costly, especially considering that the number of the logic components and clock domains on the integrated circuit continues to increase in modern integrated circuit designs.
Therefore, in order to achieve efficient testing of clock domains of the integrated circuit design, the clock domains are typically grouped into test groups. A test group is a group of domains that can be physically tested together. The test groups are manually generated by a clock designer per predetermined guidelines. The number of test groups generated by the clock designer is generally kept as small as possible in order to minimize the test time and cost. Nonetheless, the manual grouping of the clock domains is tedious, time consuming, and error prone.
For example, asynchronous domains may fail on a tester if they communicate with one another. Therefore, if asynchronous domains are placed in the same test group the integrated chip may be falsely indicated as failing. Furthermore, in a test group, there are additional constraints driving the separation of certain clocking elements that could increase noise if tested together, e.g., clocking elements may not be intended to be tested together because they create noise from too many switches being performed in the same area or domain of the integrated circuit.
Additional problems associated with or resultant from the manual grouping of clock domains include: (1) the fact that the designer for the integrated circuit may forget to list synchronous domains, or asynchronous domains that are independent, and thus potentially resulting in the improper grouping of domains; (2) timing tools typically do not list the domain crossings; (3) the grouping of multiple phase locked loops (PLLs) in a same test group may cause characterization issues, e.g., voltage speed; and (4) the grouping of multiple PLLs makes it harder to synchronize to a single tester reference clock oscillator on or off the integrated circuit.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.